1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a semiconductor device in which polysilicon is used to form source and drain regions in an initial process step so as to reduce resistance of bit lines and minimize a junction capacitance and thus improve its reliability, and a method for fabricating the same.
2. Background of the Related Art
Due to buried N+ layers (hereinafter referred to as BN+ layer), which is used in flash EEPROM cells and mask ROM cells, it is possible to make virtual ground, and the number of contact holes is diminished to reduce sizes of chips. Source and drain regions are commonly formed in a final process step in a case a semiconductor device is fabricated using BN+ layers.
A conventional method for fabricating a semiconductor device will be described with reference to FIGS. 1A to 1C which are cross-sectional views showing process steps of a method for fabricating a semiconductor device.
First, a photoresist film is coated on a semiconductor substrate 11 or a p well as shown in FIG. 1A. In this case, instead of a photoresist film 13 alone being coated, an insulating layer is first deposited on a semiconductor substrate 11 and then a photoresist film 13 is coated on the insulating layer.
Next, as shown in FIG. 1B, the photoresist film 13 over placements of BN+ layers is patterned by exposure and development processes. N+ heavily doped impurity ions are implanted into the semiconductor substrate 11 by using the photoresist pattern 13 as a mask.
Subsequently, the remaining photoresist film 13 is removed as shown in FIG. 1C. Then an annealing process is performed to grow a gate oxide layer 15 on the semiconductor substrate 11 and simultaneously form BN+ layers 17. At this time, the BN+ layers 17 function as source and drain regions. The gate oxide layer 15 is thicker on the BN+ layers than on the semiconductor substrate 11 because the BN+ layers have a high concentration of impurity ions.
According to a conventional method for fabricating a semiconductor device, source and drain regions are formed in an initial process step and gate electrodes are formed right over the source and drain regions so that it can be possible to make virtual ground and the number of contact holes in a cell is minimized to reduce the area of a chip.
However, it has following problems. There is a reduced voltage applied to bitlines in contact with BN+ layers due to a resistance of the BN+ layers. Moreover, since a junction area of the BN+ layers and a semiconductor substrate increases and thus a junction capacitance on the junction area increases, operational speed of the semiconductor device is lowered.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Therefore, the present invention is directed to a structure of a semiconductor device and a method for fabricating the same that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
An object of the invention is to provide a method for fabricating a semiconductor device in which BN+ layers are formed of doped polysilicon to be used as source and drain regions so as to reduce a resistance of bitlines and minimize a junction capacitance and thus increase its reliability.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a semiconductor device includes a semiconductor substrate, trenches formed in predetermined areas of the semiconductor substrate, an insulating layer formed beneath a surface of each of the trenches to have a recess, a polysilicon layer formed on the insulating layer in the trench, source and drain regions formed at both sides of the polysilicon layer beneath a surface of the semiconductor substrate, and gates formed over the semiconductor substrate.
In another aspect of the present invention, a method for fabricating a semiconductor device includes the steps of forming trenches in predetermined areas of a semiconductor substrate, forming a first polysilicon layer doped by impurity ions in each of the trenches, diffusing the impurity ions in the first polysilicon layer so as to form source and drain regions at both sides of each of the trenches, and forming a second polysilicon layer on the entire surface and then patterning the second polysilicon layer to form gates.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.